Sort Probe Over Current Protection Mechanism

ABSTRACT

An apparatus includes a probe card, a plurality of sort probes coupled to the probe card and detector circuitry to detect a real time over current occurrence at the sort probes.

FIELD OF THE INVENTION

The present disclosure generally relates to wafer probe testing.

BACKGROUND

In the manufacture of semiconductor devices, it is necessary that suchdevices be tested at the wafer level to evaluate their functionality.The process in which die in a wafer are tested is commonly referred toas “wafer sort.” Testing and determining design flaws at the die leveloffers several advantages. First, it allows designers to evaluate thefunctionality of new devices during development.

Increasing packaging costs also make wafer sorting a viable cost saver,in that reliability of each die on a wafer may be tested beforeincurring the higher costs of packaging. Measuring reliability alsoallows the performance of the production process to be evaluated andproduction consistency rated, such as for example by “bin switching”whereby the performance of a wafer is downgraded because that wafer'sperformance did not meet the expected criteria.

The process of die-testing and wafer sort may be carried out with awafer probe card. A probe card is an interface between an electronictest system and a semiconductor wafer. Typically the probe card ismechanically docked to a prober and electrically connected to a testerto provide an electrical path between the test system and the circuitson the wafer, thereby permitting the testing and validation of thecircuits at the wafer level, usually before they are diced and packaged.

Periodically, sort probe over current events may result in probe headdamage due to melted or recessed probes. The damaged probes must berepaired or removed to prevent improper binning. In severe instances,the entire probe head, which may be valued at several tens of thousandsof dollars, will need to be discarded as the damage is beyond repair. Incases where repair is viable, however, the repair process requiresspecially trained technicians to manually manipulate or pluck probesworking under a microscope. Thus, the repair process is labor intensiveand a production limiter as probe cards scale to tighter pitches andhigher probe counts.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates one embodiment of a test system.

FIG. 2 illustrates one embodiment of a probe card;

FIG. 3 illustrates one embodiment of a shunting e-fuse.

FIG. 4 illustrates one embodiment of a over current detectionconfiguration.

FIG. 5 is a flow diagram illustrating one embodiment for processing anover current event.

FIG. 6 illustrates one embodiment of a general-purpose electronicsystem.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of various embodiments.However, various embodiments of the invention may be practiced withoutthe specific details. In other instances, well-known methods,procedures, components, and circuits have not been described in detailso as not to obscure the particular embodiments of the invention.

Reference in the specification to “one embodiment” or “an embodiment”means that a particular feature, structure, or characteristic describedin connection with the embodiment may be included in at least animplementation. The appearances of the phrase “in one embodiment” invarious places in the specification may or may not be all referring tothe same embodiment.

FIG. 1 illustrates one embodiment of a test system 100. System 100includes an automated test equipment (ATE) system 110 implemented toperform testing on a device under test (DUT) 150. DUT 150 may be an ICdie on a wafer, or a packaged part. In one embodiment, ATE system 110 iscoupled to DUT 150 via a device interface 120 and probe card 130.

FIG. 2 illustrates another embodiment of a test system 200 in which asort probe card 130 is implemented to couple to DUT 150 via sort probes215, while being powered by a power supply 205 from an ATE system.Additionally, test system 200 includes shunting e-fuse 230, thermal fuse240, over current detector 250 and threshold detector circuit 255.

In one embodiment, shunting e-fuse 230 is coupled between a tester powersupply 205 and probes 215. In such an embodiment, e-fuse 230 protectssort probes 215 against over current event. FIG. 3 illustrates oneembodiment of shunting e-fuse 230, which includes current sense logic toindicate an over current condition.

According to one embodiment, current sense amplifier 310 includes acurrent sense amplifier 310, comparator 320 and power FET transistor330. Current sense amplifier 310 implements a current-sense resistor(R1) to convert a load current received from the ATE system to a smallvoltage and amply the voltage for output to comparator 320.

Comparator 320 compares the amplified voltage from current senseamplifier 310 to a reference voltage (Vref). If the received voltage isgreater than Vref, comparator 320 transmits a reference signal to powerFET transistor 330, which forces the power supply to shunt to ground.Thus, the power supply is forced to shut down when an over current eventis detected so that sort probes 215 are protected. In one embodiment,the circuit response time of shunting e-fuse 230 may be detuned bycomponent selection or by adding an RC delay circuit to the amplifieroutput.

Referring back to FIG. 2, thermal fuse 240 includes a thermal element isimplemented to disconnect probes 215 from power supply 205 upon beingmelted by heat attributed to an excessive current. In one embodiment,thermal fuse 240 is a fast response time 0.5A thermal fuse in series oninput/output (I/O) lines. Since I/O lines typically have a singlenon-redundant probe 215, thermal fuse 240 prevents non-repairable damageto a probe head due to an over current event. In a further embodiment,thermal fuse 240 is to be replaced after an over current occurrence.

Over current detector 250 and threshold detector circuit 255 areimplemented to detect a real time over current occurrence at probes 215.During over current events, probe temperatures of between 200C and 1500Cmay be produced, which results in a hot probe 215. Hot probes producelight within the range of detection of a photodiode. Accordingly, overcurrent detector 250 includes a photo diode placed near the probe 215array to detect infrared (IR) and visible light emission from sortprobes 215 due to joule heating.

Upon detecting IR and/or visible light, over current detector 250transmits a signal to threshold detector circuit 255, which produces asignal to be transmitted to the ATE system to indicate a probe 215 overcurrent condition. According to one embodiment, each over currentdetector 250 includes an amplifier that is monitored individually by ATEsystem I/Os via a threshold detector circuit 255. Further, the voltagemagnitude and position of each detector may be used to provide real timeinformation about the location and magnitude of the over current event.

In another embodiment, multiple current detectors 250 are routed throughthreshold detector circuits 255 and an OR-gate in order to produce alogic signal as an over current event occurs. In such an embodiment, theOR-gate or amplifier output signals are monitored with a test programthrough a tester channel or an external oscilloscope. Thus, root causedie would be identified as the over current event occurs. FIG. 4illustrates one embodiment of such a configuration.

In a further embodiment, the ATE system may be programmed to respond byshutting down power supplies 205 (105 does not appear to be defined) andproducing a bin signal or other responses that provide automatedtroubleshooting to identify the source of the over current. In yetanother embodiment, the OR-gate output may be routed directly toshunting e-fuse 230, resulting in immediate probe protection and powersupply shut down.

FIG. 5 is a flow diagram illustrating one embodiment for processing anover current event. At processing block 505, sorting is begun. Atprocessing block 510, wafers are sorted. At processing block 515 an overcurrent event is detected. At processing block 520, a visual inspectionof the sort probe array is conducted to identify an over currentlocation.

At processing block 525, sort data is reviewed for the failed die toidentify a test segment running when the burn occurred. At processingblock 525, a root cause is identified. At processing block 535, the rootcause is fixed. If no root cause is found (processing block 540), ascope test program is run while running the problem test segment on theproblem die. If the root cause continues to not be found (processingblock 550), the investigation is continued (processing block 560) untilthe root cause is identified, processing block 530.

FIG. 6 illustrates one embodiment of a computer system 600. The computersystem 600 (also referred to as the electronic system 600) as depictedcan embody a test system that includes an ATE system and a DUT toperform sequential burn-in testing.

The computer system 600 may be a mobile device such as a netbookcomputer. The computer system 600 may be a mobile device such as awireless smart phone. The computer system 600 may be a desktop computer.The computer system 600 may be a hand-held reader. The computer system600 may be a server system. The computer system 600 may be asupercomputer or high-performance computing system.

In an embodiment, the electronic system 600 is a computer system thatincludes a system bus 620 to electrically couple the various componentblocks of the electronic system 600. The system bus 620 is a single busor any combination of busses according to various embodiments. Theelectronic system 600 includes a voltage source 630 that provides powerto the integrated circuit 610. In some embodiments, the voltage source630 supplies current to the integrated circuit 610 through the systembus 620.

The integrated circuit 610 is electrically coupled to the system bus 620and includes any circuit, or combination of circuits according to anembodiment. In an embodiment, the integrated circuit 610 includes aprocessor 612 that can be of any type. As used herein, the processor 612may mean any type of circuit such as, but not limited to, amicroprocessor, a microcontroller, a graphics processor, a digitalsignal processor, or another processor.

In an embodiment, SRAM embodiments are found in memory caches of theprocessor. Other types of circuits that can be included in theintegrated circuit 610 are a custom circuit or an application-specificintegrated circuit (ASIC), such as a communications circuit 614 for usein wireless devices such as cellular telephones, smart phones, pagers,portable computers, two-way radios, and similar electronic systems, or acommunications circuit for servers.

In an embodiment, the integrated circuit 610 includes on-die memory 616such as static random-access memory (SRAM). In an embodiment, theintegrated circuit 610 includes embedded on-die memory 616 such asembedded dynamic random-access memory (eDRAM).

In an embodiment, the integrated circuit 610 is complemented with asubsequent integrated circuit 611. Useful embodiments include a dualprocessor 613 and a dual communications circuit 615 and dual on-diememory 617 such as SRAM. In an embodiment, the dual integrated circuit610 includes embedded on-die memory 617 such as eDRAM.

In an embodiment, the electronic system 600 also includes an externalmemory 640 that in turn may include one or more memory elements suitableto the particular application, such as a main memory 642 in the form ofRAM, one or more hard drives 644, and/or one or more drives that handleremovable media 646, such as diskettes, compact disks (CDs), digitalvariable disks (DVDs), flash memory drives, and other removable mediaknown in the art. The external memory 640 may also be embedded memory648 such as the first die in an embedded TSV die stack, according to anembodiment.

In an embodiment, the electronic system 600 also includes a displaydevice 650, an audio output 660. In an embodiment, the electronic system600 includes an input device such as a controller 670 that may be akeyboard, mouse, trackball, game controller, microphone,voice-recognition device, or any other input device that inputsinformation into the electronic system 600. In an embodiment, an inputdevice 670 is a camera. In an embodiment, an input device 670 is adigital sound recorder. In an embodiment, an input device 670 is acamera and a digital sound recorder.

As shown herein, the integrated circuit 610 can be implemented in anumber of different embodiments, including a test system that includesan ATE system and a DUT to perform sequential burn-in testing, and theirequivalents, an electronic system, a computer system, one or moremethods of fabricating an integrated circuit, and one or more methods offabricating an electronic assembly that includes a semiconductor diepackaged according to any of the several disclosed embodiments as setforth herein in the various embodiments and their art-recognizedequivalents. The elements, materials, geometries, dimensions, andsequence of operations can all be varied to suit particular I/O couplingrequirements including array contact count, array contact configurationfor a microelectronic die embedded in a processor mounting substrateaccording to any of the several disclosed semiconductor die packagedwith a thermal interface unit and their equivalents. A foundationsubstrate may be included, as represented by the dashed line of FIG. 6.Passive devices may also be included, as is also depicted in FIG. 6.

Although embodiments of the invention have been described in languagespecific to structural features and/or methodological acts, it is to beunderstood that claimed subject matter may not be limited to thespecific features or acts described. Rather, the specific features andacts are disclosed as sample forms of implementing the claimed subjectmatter.

1. An apparatus comprising: a probe card; a plurality of sort probescoupled to the probe card; and a shunting fuse coupled between the oneor more of the plurality of sort probes and a power supply to protectthe one or more of the plurality of sort probes against an over currentevent.
 2. The apparatus of claim 1 wherein the shunting fuse comprises acomparator to compare a received voltage to a reference voltage andgenerate a reference signal upon detecting that the received voltage isgreater than the reference voltage.
 3. The apparatus of claim 2 whereinthe shunting fuse further comprises a transistor to shunt the powersupply to ground in response to receiving the reference signal.
 4. Theapparatus of claim 3 wherein the shunting fuse further comprises: aresistor to convert a load current to a small voltage; and a currentsense amplifier to amplify the small voltage to the received voltage. 5.The apparatus of claim 1 further comprising a thermal fuse to disconnectthe one or more of the plurality of sort probes from the power supplyupon the occurrence of an excessive current.
 6. The apparatus of claim 5wherein the thermal fuse is a fast response fuse. 7-15. (canceled)
 16. Atest system comprising: an automated test equipment (ATE) system; aprobe card coupled to the ATE system; a plurality of sort probes coupledto the probe card; and an integrated circuit (IC) device coupled theprobe card via the plurality of sort probes; and a shunting fuse coupledbetween the one or more of the plurality of sort probes and the ATEsystem to protect the one or more of the plurality of sort probesagainst an over current event.
 17. The test system of claim 17 whereinthe shunting fuse comprises a comparator to compare a received voltageto a reference voltage and generate a reference signal upon detectingthat the received voltage is greater than the reference voltage.
 18. Thetest system of claim 17 wherein the shunting fuse further comprises atransistor to shunt the power supply to ground in response to receivingthe reference signal.
 19. The test system of claim 18 wherein theshunting fuse further comprises: a resistor to convert a load currentfrom the ATE system to a small voltage; and a current sense amplifier toamplify the small voltage to the received voltage.
 20. The test systemof claim 16 further comprising a thermal fuse to disconnect the one ormore of the plurality of sort probes from the ATE system power supplyupon the occurrence of an excessive current. 21-29. (canceled)
 30. Thetest system of claim 20 wherein the thermal fuse is a fast responsefuse.